Yield enhancement in the routing phase of integrated circuit layout synthesis

Author

Tyagi, Aakash ; Bayoumi, M. ; Manthravadi, Praneetha

Author_Institution

Dept. of Electr. & Comput. Eng., Southwestern Louisiana Univ., Lafayette, LA, USA

fYear

1994

fDate

19-21 Jan 1994

Firstpage

52

Lastpage

60

Abstract

An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms

Keywords

circuit layout CAD; integrated circuit technology; network routing; IC layout; critical area reduction; defect tolerant features; defect tolerant routing algorithms; detailed routing; final track assignment; integrated circuit layout synthesis; net merging; routing phase; yield enhancement; Costs; Design automation; Electronics industry; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit synthesis; Integrated circuit yield; Manufacturing automation; Merging; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-1850-1

Type

conf

DOI

10.1109/ICWSI.1994.291264

Filename

291264