Title :
A-VMCO: A novel forming-free, self-rectifying, analog memory cell with low-current operation, nonfilamentary switching and excellent variability
Author :
Govoreanu, B. ; Crotti, D. ; Subhechha, S. ; Zhang, L. ; Chen, Y.Y. ; Clima, S. ; Paraschiv, V. ; Hody, H. ; Adelmann, C. ; Popovici, M. ; Richard, O. ; Jurczak, M.
Author_Institution :
imec, Leuven, Belgium
Abstract :
We demonstrate a self-rectifying, compliance-free, BEOL CMOS-compatible, resistive switching memory device, with nonfilamentary switching mechanism, forming-free operation, analog switching behavior and excellent device to device operation uniformity, down to the smallest device size. The cells have a reset switching current density of ~0.3MA/cm2 (and ~10× lower set current). This corresponds to ~5uA reset current in a 40nm-size cell, projecting down to 1uA for a 20nm-size. The switching currents are tunable by process and structural cell design. The cells can be operated with pulses as short as 10ns, at below ±7V. Cycling for at least 106cy and retention of 55°C/3yr are demonstrated, with clear paths for further improvement. These key features are enabled by the use of an amorphous-Silicon (a-Si) barrier layer, which acts as a semi-insulating oxygen scavenger in a dual-layer a-Si/TiO2 active stack, being able to provide nonlinear IV cell characteristics, as well as to induce a large oxygen vacancy density in the switching layer.
Keywords :
CMOS memory circuits; amorphous semiconductors; analogue storage; current density; resistive RAM; silicon; titanium compounds; BEOL CMOS-compatible resistive switching memory device; Si; TiO2; a-Si barrier layer; amorphous-silicon barrier layer; analog switching behavior; current 1 muA; dual-layer a-Si-TiO2 active stack; forming-free operation; nonfilamentary switching mechanism; oxygen vacancy density; process design; reset switching current density; self-rectifying compliance-free resistive switching memory device; semi-insulating oxygen scavenger; size 20 nm; size 40 nm; structural cell design; switching layer; time 10 ns; Annealing; Arrays; Electrodes; Resistance; Switches; Switching circuits; Tin;
Conference_Titel :
VLSI Technology (VLSI Technology), 2015 Symposium on
Conference_Location :
Kyoto
DOI :
10.1109/VLSIT.2015.7223717