DocumentCode :
1858568
Title :
Low power and high performance MOSFET
Author :
Boopathy E, Veera ; Raghul, G. ; Karthick, K.
Author_Institution :
VLSI Design, V.S.B. Eng. Coll., Karur, India
fYear :
2015
fDate :
8-10 Jan. 2015
Firstpage :
1
Lastpage :
5
Abstract :
To analysis leakage current and delay for Double Gate MOSFET with Single gate MOSFET at 45nm in CMOS Technology by using the Cadence Virtuoso simulation tool. When compared to single gate MOSFET, the leakage current and delay are observed to be reduced in double gate MOSFET. The drive current remains the same for both single and double gate MOSFET based on Vgs but the short channel characteristics of double gate MOSFET gets improved. Double gate MOSFET is mostly recommended for low power and high performance application. When compared to bulk Si single gate device, the total power utilization of inverter, static, dynamic circuit and latch by using double gate demonstrates that leakage current and delay reduced by a factor of over 10X.
Keywords :
CMOS integrated circuits; MOSFET; leakage currents; low-power electronics; semiconductor device models; CMOS; Cadence Virtuoso simulation tool; double gate MOSFET; dynamic circuit; inverter; latch; leakage current; single gate MOSFET; size 45 nm; CMOS integrated circuits; CMOS technology; Inverters; Leakage currents; Logic gates; MOSFET; Switches; DIBL; Delay; Double Gate MOSFET; Inverter; Latch; Leakage Current;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4799-7925-7
Type :
conf
DOI :
10.1109/VLSI-SATA.2015.7050455
Filename :
7050455
Link To Document :
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