FPGA implementation of an advanced encoding and decoding architecture of polar codes

Polar code, newly formulated by Erdal Arikan, has got a wide recognition from the information theory community. Polar code achieves the capacity of the class of symmetric binary memory less channels. In this paper, we propose efficient hardware architecture on a FPGA platform using Xilinx Virtex VI for implementing the advanced encoding and decoding schemes. The performance of the proposed architecture out performs the existing techniques such as: successive cancellation decoder, list successive cancellation, belief propagation etc; with respect to bit error rate and resource utilization.