• DocumentCode
    1858807
  • Title

    Intertwined scheduling, module selection and allocation in time-and-area constrained synthesis

  • Author

    Harris, I.G. ; Orailoglu, A.

  • Author_Institution
    University of California
  • fYear
    1993
  • fDate
    3-6 May 1993
  • Firstpage
    1682
  • Lastpage
    1685
  • Keywords
    Clocks; Control system synthesis; Delay; Hardware; High level synthesis; Libraries; Processor scheduling; Resource management; Scheduling algorithm; Time factors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
  • Conference_Location
    IEEE
  • Print_ISBN
    0-7803-1281-3
  • Type

    conf

  • Filename
    692990
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1858807