Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation

After the invention of carbon nanotube field effect transistor (CNTFET) in 1998 it has attracted a number of research groups. It plays a great role in design of digital circuits to provide higher speed, low power consumption and less delay. One of its major advantages is that we can change its threshold voltage by changing its diameter. The volume of the channel region, which is the most important portion for carrier transport, can be adjusted by changing the diameter of the carbon nanotue (CNT). In many research papers the channel volume is also adjusted by putting more than one CNT in the channel region. In this paper we have made an extensive study of both the cases. We have considered both type of arrangements to obtain almost equal channel volume for carrier transport and used them to design logic circuits like inverter, two input nand gate and two input nor gate. We have then calculated delay, power and delay power product for all the circuits using HSPICE and finally compared the results. From the comparison we found that the use of a single CNT with larger diameter than the use of multiple CNTs with smaller diameters is giving up to 60% less delay and reduction of power delay product up to 80%.