Signal processing for multiGigabit communication

The sophisticated digital signal processing (DSP) at the core of modern communication receivers implicitly assumes the availability of accurate analog-to-digital converters (ADCs). As communication speeds scale up, however, high-rate, high-precision ADCs are either not available, or are too costly or power-hungry. In this paper, we survey our recent results on DSP-centric receiver design with sloppy ADCs. For applications requiring limited dynamic range (e.g., small constellations over line-of-sight channels), we consider the performance achievable with ADCs whose precision is drastically smaller (e.g., 1-4 bits) than those in current practice (e.g. 8-12 bits), with a view to characterizing information-theoretic limits as well as developing practical receiver algorithms. For applications requiring larger dynamic range (e.g., large constellations and/or dispersive channels), we consider receiver architectures centered around time-interleaved ADCs, addressing the mismatch between the parallel ADCs for the specific context of their use within a communication receiver, with a view to preventing error floors in receiver performance.