Title :
Performance analysis of various scheduling algorithms using FPGA platforms
Author :
Nazir, Liyaqat ; Mir, Roohie Naaz
Author_Institution :
Comput. Sci. Eng., Nat. Inst. of Technol., Srinagar, India
Abstract :
This paper discusses the synthesis and implementation of various scheduling algorithms for Network-on-Chip communication. Traditionally these scheduling algorithms were implemented on ASIC platforms generally for shared bus based interconnection systems. In this paper we carry a comparative analysis by synthesizing and implementing various scheduling algorithms for configuring the crossbar in input queued switches. The implementation is carried out using various arbitration networks responsible for scheduling 8-bit input requests. The implementation targets Spartan6 FPGA family. The analysis concludes that the scheduling algorithm based on CLA based encoding network shows lower power delay product and lower area delay product and a reasonably lower resource utilization when implemented for speed optimization goal.
Keywords :
application specific integrated circuits; field programmable gate arrays; integrated circuit design; integrated circuit interconnections; network-on-chip; scheduling; ASIC platforms; CLA based encoding network; FPGA platforms; Spartan6 FPGA family; area delay product; crossbar; input queued switches; input request scheduling; network-on-chip communication; performance analysis; power delay product; resource utilization; scheduling algorithms; shared bus based interconnection systems; speed optimization; word length 8 bit; Algorithm design and analysis; Clocks; Encoding; Field programmable gate arrays; Logic gates; Scheduling algorithms; Switches; Network-on-chip; PPE; arbiter; scheduling;
Conference_Titel :
VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4799-7925-7
DOI :
10.1109/VLSI-SATA.2015.7050477
