DocumentCode
1859455
Title
Testability modeling usage in design-for-test and product lifecycle cost reduction
Author
Valfre, James
Author_Institution
Syst. Test Directorate, Raytheon Missile Syst., Tucson, AZ, USA
fYear
2012
fDate
10-13 Sept. 2012
Firstpage
39
Lastpage
41
Abstract
Weapon systems have become increasingly complex and customer funding has become constricted. Customers and contractors are in an environment where the cost of test systems has to be reduced yet still test effectively in order to remain competitive. In an effort to reduce the total development and lifecycle cost, companies are using Design-For-Test (DFT) methodologies to increase Built-In-Test (BIT) coverage and reduce the need for external Special Test Equipment (STE). Using test coverage analysis tools during prime hardware design efforts has benefits including identification of gaps in test capability, increased test coverage, test strategy optimization, increased accessibility, fault isolation and a reduction in overall test cost. This paper will explore the concept of testability modeling and how it can be applied to maximize system test coverage, derive STE and BIT requirements and provide increased circuit accessibility for usage in DFT considerations. Test modeling tools enable designers to formulate test coverage and testability analysis that assists in identification of suggested hardware design improvements in order to gain greater test coverage. The tools facilitate an iterative analysis of designs at multiple assembly levels and at different design maturities and can allow for designers and test engineers to relate functional test coverage, fault coverage and fault isolation to varying test cases such as production acceptance and design verification testing. Output of the testability model can assist in optimization of test strategies as well as provide insight into failure rates and failure modes with the inclusion of reliability data. Used as part of the design iteration, this process can be repeated at different design and verification stages to produce a product which provides circuitry access to test itself, maximize test coverage while minimizing test equipment, and predict failure modes and identify line replaceable units (LRUs). Testability mode- ing can significantly reduce the cost of test equipment development, lifecycle cost and recurring unit production cost thus making the product more affordable to build, deliver and deploy.
Keywords
automatic test equipment; built-in self test; cost reduction; design for testability; failure analysis; iterative methods; optimisation; product life cycle management; reliability; weapons; BIT; DFT; LRU; STE; assembly level; built-in-test; design for test; design iteration; design verification testing; fault coverage; fault isolation; iterative analysis; line replaceable units; product lifecycle cost reduction; reliability; special test equipment; test equipment development; test modeling tool; test strategy optimization; testability modeling; unit production cost recurring; weapon system; Assembly; Circuit faults; Discrete Fourier transforms; Integrated circuit modeling; Optimization; Test equipment; Build-in-Test; Design-For-Test; accessibility; controllability; functional test; lifecycle cost reduction; observability; structural test; test modeling; test strategy optimization; testability; testability analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
AUTOTESTCON, 2012 IEEE
Conference_Location
Anaheim, CA
ISSN
1088-7725
Print_ISBN
978-1-4673-0698-0
Type
conf
DOI
10.1109/AUTEST.2012.6334543
Filename
6334543
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