Title :
Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA
Author :
Kumar M, Vinay ; Selvakumar A, David ; Sobha, P.M.
Author_Institution :
Secure Hardware & VLSI Design Group, CDAC, Bangalore, India
Abstract :
This paper presents a Fast Fourier Transform (FFT) processor optimized for both `area´ and `frequency´. The processor architecture is deeply pipelined Radix-2 butterfly unit, 1024 point, 64bit Fixed Point input with 32bit real and 32bit imaginary, Decimation In Time (DIT) FFT processor on Field Programmable Gate Array (FPGA). The proposed architecture is based on Dual RAM Ping-Pong Burst I/O with efficient addressing techniques which clocks at 385.804MHz on Xilinx Virtex-6 xc6vlx550t-2ff1759 taking 16.376μs to calculate one set of 1024 point FFT.
Keywords :
fast Fourier transforms; field programmable gate arrays; fixed point arithmetic; pipeline arithmetic; DIT FFT processor; Dual RAM Ping-Pong Burst I-O; FPGA; Xilinx Virtex-6 xc6vlx550t-2ff1759; decimation In time FFT processor; deeply pipelined Radix-2 butterfly unit; fast Fourier transform processor; field programmable gate array; fixed point input; frequency 385.804 MHz; processor architecture; storage capacity 64 bit; word length 32 bit; Digital signal processing; Discrete Fourier transforms; Generators; Indexes; Indium tin oxide; Random access memory; Table lookup; 1024-point FFT; 64bit Fixed Point Arithmetic; CORDIC; FFT processor; FPGA; Ping-Pong operation; Radix-2 Butterfly; Verilog HDL; Virtex-6;
Conference_Titel :
VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4799-7925-7
DOI :
10.1109/VLSI-SATA.2015.7050487
