Robust detection of soft errors using delayed capture methodology

With the scaling of technology node and voltage levels, the susceptibility of logic to soft errors is increasing. Hence it is very important to take care of soft errors in the combinational logic along with those in the sequential elements. In this paper, a novel method is proposed to detect the presence of soft errors in both combinational and sequential logic. In this method, flip-flops are grouped and parity is computed for each group twice - once at the input of the flip-flops and next at the output. Later, the parity at the inputs and outputs is compared to detect the presence of soft errors. The effectiveness of the technique is shown through experimental results.