FPGA prototyping of energy dispersal and improved error efficiency techniques for DVB-satellite standard

This paper presents the real time FPGA prototyping of energy dispersal technique i.e. Scrambler/De-Scrambler and improved error efficiency technique i.e. Interleaver/De-Interleaver of the digital video broadcasting satellite standard. These modules are designed using verilog HDL and integrated back-to-back i.e. scrambler and interleaver for transmitter and de-scrambler and de-interleaver for receiver. These integrated blocks are prototyped on commercially available Xilinx virtex xc5vlx110t-1 FPGA device. Further synthesis results are reported and experimented results are validated using logic analyzer.