Arithmetic compaction circuits for mixed-signal systems testing

Arithmetic error-control codes (ECCs) have been designed to protect the integrity of data being transmitted and/or processed. The implementation of an ECC involves constructing an appropriate encoding/decoding device. An important part of this device is a residue computing circuit (RCC). This circuit has also been used in mixed-signal systems testing and is referred to as a compaction circuit. As ECCs originated primarily to protect data transfers over binary channels, the design methodology for RCCs has been mostly oriented toward a binary case. A non-binary design technique has only been reported for a special type of compaction modulus. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. It is assumed that the codes being compacted are fuzzy, which distorts the result of compaction and increases the aliasing rate. Even though the fault free system´s output code distortion is small, the compaction circuit may aggravate it beyond the acceptable levels making the method impractical. We design a low cost compactor that does not increase the code distortion. The circuit can be used for off-line and on-line mixed-signal systems testing, as well as fault-tolerant data processing and noise-tolerant data transmission.