Evaluation of concurrent error detection techniques on the advanced encryption standard

Due to the shrinking of transistors dimensions in nowadays technologies, circuits are more and more sensitive to aging phenomenon, as well as soft errors. Furthermore cryptographic circuits are prone to fault attacks, which intend to retrieve secret data by mean of fault injection. Thus, concurrent fault detection is of prime interest for such crypto devices. The purpose of this paper is to compare several concurrent fault detection schemes dedicated to the hardware implementation of the advanced encryption standard. The schemes under comparison are directly issued from the literature or built from several complementary solutions. The evaluation of these schemes is performed in terms of costs and performance with particular emphasis on errors vs faults detection capabilities.