Architecting high-throughput PXI systems

With the PC industry evolving from PCI to PCI Express in late 2005, the PXI industry was able to take advantage of this increase in available bus bandwidth and subsequently introduced the PXI Express specification. The PCI Express bus continues to evolve, while maintaining backwards compatibility, with the release of PCI Express 2.0 in 2010, and the PXI Express platform performance follows. These advancements enable PXI to meet the requirements of test and measurement applications that demand high data throughput capabilities. At the same time, they can problematically add a level of complexity to system architectures that require these increased bus capacities. Most noticeably, PCI Express technology has enabled high-speed data streaming architectures where data transfer between instrument and memory occurs at a rate on the order of gigabytes per second. Applications that require this capability include RF record and playback, noise mapping, and algorithm prototyping. At the same time PCI Express has also enabled the PXI platform products like chassis and controllers to support the back-end of high performance PXI instrumentation where acquisition sample rates and signal bandwidths on the order of gigahertz are common. With the introduction of Field Programmable Gate Arrays (FPGAs) for test, came the need to communicate between PXI modules in a more direct form, from which peer-to-peer streaming was born. Combining all of these technologies enabled by PCI Express, peer-to-peer streaming between high performance instrumentation and an FPGA module co-processor can significantly reduce the time required to return a complex measurement. As PXI test and measurement systems continue to grow in this direction it becomes increasingly important to understand the components of high throughput systems and the considerations that must be taken to ensure bottlenecks are not created. An evaluation of system bandwidth capabilities must account for all of the communication links,- from the instrumentation analog front-end to the capacities of data storage memory.