Asynchronous logical system simulation in VHDL

Author

Kovac, Michal ; Kubicek, Michal

Author_Institution

Dept. of Radio Electron., Brno Univ. of Technol., Brno

fYear

2008

fDate

24-25 April 2008

Firstpage

1

Lastpage

4

Abstract

The following article describes the fundamentals of asynchronous logical systems from handshaking protocols to Muller pipeline. Understanding these fundamentals is important to analysing problems. The aim of this article is to solve problems with the design and simulation of asynchronous circuits. The final results are simulation models of a 4-phase bundled-data pipeline and a 4-phase dual-rail pipeline. The simulation models were generated in the simulation tool Modelsim with real gate delays and with zero wire delays.

Keywords

asynchronous circuits; circuit simulation; hardware description languages; logic simulation; pipeline processing; 4-phase bundled-data pipeline; 4-phase dual-rail pipeline; Modelsim; Muller pipeline; asynchronous circuits; asynchronous logical system simulation; handshaking protocols; real gate delays; zero wire delays; Asynchronous circuits; Circuit simulation; Clocks; Delay; Design automation; Design methodology; Hazards; Pipelines; Protocols; Wire; Asynchronous; Muller pipeline; VHDL;

fLanguage

English

Publisher

ieee

Conference_Titel

Radioelektronika, 2008 18th International Conference

Conference_Location

Prague

Print_ISBN

978-1-4244-2087-2

Electronic_ISBN

978-1-4244-2088-9

Type

conf

DOI

10.1109/RADIOELEK.2008.4542725

Filename

4542725