The practical realities of high-speed digital test in a production environment

The challenges of test development and system setup using Automated Test Equipment (ATE) change when transitioning from a world where clock and data are transmitted separately on wide parallel buses to a world where the clock is embedded in data transmitted on fewer high-speed serial lanes. Parallel buses transmit and receive data with a synchronous clock and typically operate at data rates less than 1Gb/s. The challenges in meeting timing requirements for large high-speed parallel buses have limited the growth of parallel bus standards. These challenges have brought a growth in high-speed serial bus standards. Both parallel and serial data transmission come with system design challenges. ATE designed to test high-speed parallel and serial buses includes features to minimize design challenges for the test engineer. This paper discusses critical features in ATE that enable reliable testing of parallel buses with synchronous clocks as well as serial buses with embedded clocks.