Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories

Error correction codes combined with built-in current sensors (BICS) have been proposed as an effective technique to detect and correct SEU errors in memories. As technology scales down, multiple bit upsets affecting the same word are becoming more common as cell density increases. In this work we propose a Cross-BICS monitoring architecture to enhance SEU detection and correction in SRAM memories. The proposed architecture uses two types of BICS: one monitors the same-row cells (through power lines), while the other monitors the same-column cells (through bit lines).