RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip

In the context of the emerging 3D integration paradigm, chips are built as stacks of several (likely heterogeneous) 2D layers. The topology of their communication network is quite irregular, mainly due to the different topologies of the 2D layers and the partial vertical connection between these layers. In this paper, a reconfigurable inter-layer routing mechanism (RILM) for such topologies is proposed. We firstly present the mechanism of composing the routing algorithms in different layers, through the vertical links, in order to achieve a multi-layer routing algorithm. Reconfiguration of the routing can be done for multiple reasons: to achieve fault-tolerant capability, but also under dynamic changing of the communication requirements, or, simply, to avoid congestions. To obtain a complete routing reconfiguration for the entire stack of layers, we propose a reconfiguration algorithm of the inter-layer routes, as a complement to the 2D routing reconfiguration. Additionally, independently of the 2D routing algorithm properties, RILM tolerates multiple failures of vertical links, as long as the stack of layers is not partitioned.