DocumentCode
1860500
Title
The UCSC Kestrel high performance SIMD processor: present and future
Author
Mesa-Martinez, Francisco ; Perlman, Eric ; Hughey, Richard
Author_Institution
Jack Baskin Sch. of Eng., California Univ., Santa Cruz, CA, USA
Volume
3
fYear
2001
fDate
2001
Abstract
The UCSC Kestrel parallel processor is a single-board linear array processor with 512 8-bit processing elements. In the process of building the machine, the authors have touched nearly all aspects of computer engineering, from VLSI layout to board design and debugging, and from device drivers to new algorithm development. The programmable array is primarily designed for several core algorithms from computational biology, on which Kestrel can outperform a workstation by a factor of 20. They have also considered a variety of other algorithms, including graph coloring, computational chemistry and neural network evaluation
Keywords
VLSI; computer science education; educational courses; graph colouring; parallel processing; programmable logic arrays; 8 bit; SIMD; UCSC Kestrel parallel processor; USA; VLSI layout; algorithm development; board debugging; board design; computational biology; computational chemistry; computer architecture; computer engineering; core algorithms; device drivers; graph coloring; neural network evaluation; parallel processing; programmable array; single-board linear array processor; undergraduate research; Algorithm design and analysis; Biology computing; Buildings; Chemistry; Computational biology; Computer networks; Debugging; Design engineering; Very large scale integration; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Frontiers in Education Conference, 2001. 31st Annual
Conference_Location
Reno, NV
ISSN
0190-5848
Print_ISBN
0-7803-6669-7
Type
conf
DOI
10.1109/FIE.2001.964045
Filename
964045
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