DocumentCode
1860573
Title
Probabilistic methods for the impact of an SET in combinational logic
Author
Gangadhar, Sreenivas ; Tragoudas, Spyros
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL, USA
fYear
2010
fDate
5-7 July 2010
Firstpage
41
Lastpage
46
Abstract
A novel method is proposed in order to calculate the probability of an SET resulting into SEU. The method is proposed to calculate the propagation of SET to the output gate at any time instant within the latching window. The method uses symbolic simulation and disjoint covers of appropriately formulated functions to take into consideration re-convergent paths and therefore more accurate calculations. This is evaluated experimentally on the benchmark circuits.
Keywords
combinational circuits; integrated circuit testing; logic testing; probability; SET propagation; combinational logic; latching window; output gate; probabilistic method; reconvergent path; single event transient; single event upset; symbolic simulation; Boolean functions; Data structures; Delay; Equations; Integrated circuit modeling; Logic gates; Probability;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International
Conference_Location
Corfu
Print_ISBN
978-1-4244-7724-1
Type
conf
DOI
10.1109/IOLTS.2010.5560234
Filename
5560234
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