Temperature dependence of NBTI induced delay

Negative Bias Temperature Instability (NBTI) has become a major reliability concern for nanoscaled PMOS transistors. NBTI is a thermally activated process and its aftereffects (e.g. threshold voltage shift, current degradation and delay increment) increase exponentially with the rise in temperature. This paper presents a model of temperature impact on NBTI induced delay for PMOS transistor. It demonstrates the model on 90nm, 65nm and 45nm Predictive Technology Model (PTM) designs operating at temperature range 25-125°C. The results show a strong correlation of NBTI induced delay with threshold voltage shift and holes mobility degradation. The key insights observed are: (a) NBTI induced threshold voltage shift is temperature sensitive and increases up to 42% at high temperatures, (b) NBTI degrades holes mobility in PMOS inversion layer and the degradation reaches 8% in 45nm technology and (c) The impact of NBTI on PMOS transistor delay becomes significant at high temperature and increases by approximately 2.5% in each successive technology reaching 11.5% in 45nm technology.