DocumentCode
1860733
Title
A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC
Author
Lee, Chun C. ; Flynn, Michael P.
Author_Institution
Dept. of EECS, Univ. of Michigan, Ann Arbor, MI, USA
fYear
2010
fDate
16-18 June 2010
Firstpage
239
Lastpage
240
Abstract
A 12b 50MS/s ADC is presented that pipelines a first stage 6b MDAC with a second stage 7b SAR ADC. The first stage uses a low-power SAR architecture for the sub-ADC, to achieve the large 6b stage resolution. A “half-gain” MDAC reduces the output swing and increases the closed-loop bandwidth of the op-amp in the first stage. This ADC consumes 3.5mW from a 1.3V supply, achieves an ENOB of 10.4b at Nyquist, and an FOM of 52fJ/conversion-step.
Keywords
analogue-digital conversion; low-power electronics; operational amplifiers; SAR assisted 2-stage pipeline ADC; closed-loop bandwidth; half-gain MDAC; low-power SAR architecture; op-amp; power 3.5 mW; voltage 1.3 V; word length 12 bit; word length 6 bit; word length 7 bit; Bandwidth; CMOS integrated circuits; Capacitors; Noise; Pipelines; Power demand; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-5454-9
Type
conf
DOI
10.1109/VLSIC.2010.5560243
Filename
5560243
Link To Document