1.4µW/channel 16-channel EEG/ECoG processor for smart brain sensor SoC

Author

Chen, Tung-Chien ; Lee, Tsung-Hsueh ; Chen, Yu-Hsin ; Ma, Tsung-Chuan ; Chuang, Tzu-Der ; Chou, Chien-Jung ; Yang, Chung-Hsing ; Lin, Tsung-Hsien ; Chen, Liang-Gee

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2010

fDate

16-18 June 2010

Firstpage

21

Lastpage

22

Abstract

A 16-channel smart brain sensor SoC is proposed with the integrated digital EEG/ECoG processor (DEEP) to perform multi-dimension feature space analysis algorithms. The DEEP has three processing pipelines to filter out the artifacts, extract the multi-domain features, and interpret the inherent meanings according to the applications. Dedicated accelerators as well as a RISC are embedded to provide efficient computation and flexibility. Processing folding among channels saves the dominating leakage power. 1.4 μW/channel power is achieved after the implementation in 90 nm process.

Keywords

brain-computer interfaces; electroencephalography; reduced instruction set computing; system-on-chip; 16-channel EEG/ECoG processor; 16-channel smart brain sensor SoC; RISC; integrated digital EEG/ECoG processor; multidimension feature space analysis; multidomain features; power 1.4 muW; Algorithm design and analysis; Electroencephalography; Feature extraction; Iron; Pipelines; Reduced instruction set computing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-5454-9

Type

conf

DOI

10.1109/VLSIC.2010.5560258

Filename

5560258