Small-defect detection in sub-100nm SRAM cells using a WL-pulse timing-margin measurement scheme

Author

Morita, Yasuhiro ; Nose, Koichi ; Noguchi, Koichiro ; Takami, Shinya ; Goto, Kenji ; Aimoto, Yoshiharu ; Kimura, Akira ; Mizuno, Masayuki

Author_Institution

Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan

fYear

2010

fDate

16-18 June 2010

Firstpage

37

Lastpage

38

Abstract

The detection of small defects in an SRAM cell with our WL-pulse timing-margin measurement scheme has been demonstrated on a 90nm 2Mb SRAM. WL-width control with a high resolution of 24.1ps and a wide range improves the sensitivity of detection for delay and SNM variations with only a 0.6% area overhead, and statistical analysis makes possible the detection of small-delay defects that, in conventional testing, would be buried due to delay variations in peripheral circuitry.

Keywords

SRAM chips; delay circuits; statistical analysis; SNM variation; SRAM cell; WL-pulse timing-margin measurement; WL-width control; delay variation; peripheral circuitry; size 100 nm; size 90 nm; small-delay defect detection; statistical analysis; Binary codes; Delay; Generators; Random access memory; Statistical analysis; Synchronization; SRAM test; WL-pulse timing margin; small defect;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-5454-9

Type

conf

DOI

10.1109/VLSIC.2010.5560264

Filename

5560264