New power saving design method for CMOS flash ADC

Author

Tsai, Chia-Chun ; Hong, Kai-Wei ; Hwang, Yuh-Shyan ; Lee, Wen-Ta ; Lee, Trong-Yen

Author_Institution

Inst of Comput., Commun. & Control, Nat. Taipei Univ. of Technol., Taiwan

Volume

3

fYear

2004

fDate

25-28 July 2004

Abstract

A new power saving design method for CMOS flash ADC is presented. With an inverter as a comparator along with an NMOS and a PMOS as switches, we use bisection method to let only half of comparators in flash ADC working in every clock cycle. An example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in power consumption.

Keywords

CMOS digital integrated circuits; SPICE; analogue-digital conversion; circuit simulation; integrated circuit design; power integrated circuits; 200 MHz; 3.3 V; 40.75 mW; CMOS flash ADC; HSPICE simulation; NMOS switches; PMOS switches; bisection method; comparator; inverter; power consumption; power saving design method; Analog-digital conversion; Circuit simulation; Clocks; Communication system control; Design methodology; Energy consumption; Error correction codes; Inverters; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354372

Filename

1354372