• DocumentCode
    1861672
  • Title

    Scalable, sub-1W, sub-10ps clock skew, global clock distribution architecture for Intel® Core™ i7/i5/i3 microprocessors

  • Author

    Shamanna, Guru ; Kurd, Nasser ; Douglas, Jonathan ; Morrise, Matthew

  • Author_Institution
    Intel Corp., Hillsboro, OR, USA
  • fYear
    2010
  • fDate
    16-18 June 2010
  • Firstpage
    83
  • Lastpage
    84
  • Abstract
    This paper describes global clock distribution architecture of Intel® Core™ i7/i5/i3 microprocessor family. Highlight of this paper is a pseudo-recombinant clock distribution architecture successfully implemented in 32nm/45nm generation of Core™ i7/i5/i3 processors. This clock distribution topology achieves less than 10ps clock skew while consuming a maximum power of 1 Watt across entire operating voltage and frequency range.
  • Keywords
    clock distribution networks; computer architecture; electronic engineering computing; microprocessor chips; Intel® Core™; clock distribution topology; clock skew; global clock distribution architecture; i3 microprocessor; i5 microprocessor; i7 microprocessor; operating frequency range; operating voltage; pseudo-recombinant clock distribution architecture; Clocks; Delay; Integrated circuit interconnections; Layout; Microprocessors; Phase locked loops; Topology; Clock Distribution; Intel®; Power; Skew; Spine;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560279
  • Filename
    5560279
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1861672