DocumentCode :
1861902
Title :
A hierarchical placement method for standard cell layout based on wire length driven clustering
Author :
Kubota, Hajime ; Wakabayashi, Shinichi ; Koide, Tetsushi
Author_Institution :
Dept. of Artificial Complex Syst. Eng., Hiroshima Univ., Japan
Volume :
3
fYear :
2004
fDate :
25-28 July 2004
Abstract :
This paper presents a new hierarchical placement method for standard cell layout. The proposed method consists of three phases, clustering of cells, hierarchical global cluster placement, and detailed cell placement. First, a set of clusters is constructed considering their internal structures. When cluster placement is determined based on simulated annealing, the wire length between clusters is estimated based on the structural information of each cluster so as to produce a good cluster placement. In the detailed cell placement phase, cells are placed in rows according to the global cluster placement, and cell placement is iteratively improved to get a final cell placement. Experimental results based on benchmark data demonstrate the effectiveness of the proposed method.
Keywords :
circuit layout CAD; integrated circuit layout; simulated annealing; cell clustering; hierarchical global cluster placement; integrated circuit layout; simulated annealing; standard cell layout; wire length driven clustering; Circuits; Law; Modeling; Partitioning algorithms; Process design; Routing; Simulated annealing; Systems engineering and theory; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
Type :
conf
DOI :
10.1109/MWSCAS.2004.1354385
Filename :
1354385
Link To Document :
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