A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Author

Bae, Seung-Jun ; Sohn, Young-Soo ; Oh, Tae-Young ; Kwak, Sang-Hyup ; Kim, Dong-Min ; Kim, Dae-Hyun ; Kim, Young-Sik ; Yang, Yoo-Seok ; Doo, Su-Yeon ; Lee, Jin-Il ; Bang, Sam-Young ; Park, Sun-Young ; Yeom, Ki-Woong ; Lee, Jae-Young ; Park, Hwanwook ; Kim,

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2010

fDate

16-18 June 2010

Firstpage

193

Lastpage

194

Abstract

A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40 nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670 fs RMS. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to the integrating DFE. Moreover, on-chip de-emphasis circuit in TX multiplexer reduces ISI of both on and off chip.

Keywords

DRAM chips; clocks; intersymbol interference; jitter; phase locked loops; transceivers; ISI reduction techniques; LC PLL; Q-inductor; RX 2-tap hybrid DFE; TX multiplexer; bit rate 7 Gbit/s; clock tree regulator; closed loop replica path; high frequency noise; high-speed DRAM interface; integration methods; jitter; on-chip de-emphasis circuit; sampling method; single-ended transceiver; size 40 nm; Decision feedback equalizers; Jitter; Noise; Phase locked loops; Random access memory; Regulators; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-5454-9

Type

conf

DOI

10.1109/VLSIC.2010.5560300

Filename

5560300