Title :
A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110µsec
Author :
Chun, Ki Chul ; Jain, Pulkit ; Kim, Tae-Ho ; Kim, Chris H.
Author_Institution :
Dept. of ECE, Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.
Keywords :
CMOS memory circuits; DRAM chips; CMOS process; asymmetric 2T gain cell embedded DRAM; current sensing scheme; frequency 667 MHz; logic compatible embedded DRAM; pseudo-PMOS diode; random cycle; size 65 nm; time 110 mus; voltage 1.1 V; Computer architecture; Logic gates; MOS devices; Microprocessors; Sensors; Time measurement; Transistors;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560303
