Title :
Resonant supply noise canceller utilizing parasitic capacitance of sleep blocks
Author :
Kim, Jinmyoung ; Nakura, Toru ; Takata, Hidehiro ; Ishibashi, Koichiro ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper proposes a resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. It has small area penalty because we use sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18μm CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.
Keywords :
CMOS integrated circuits; integrated circuit noise; integrated circuit testing; power aware computing; CMOS process; abrupt supply voltage switching; abrupt wake-up; dynamic voltage scaling; noise cancelling; parasitic capacitance; power gating; power mode switching; resonant supply noise canceller; size 0.18 mum; sleep blocks; supply noise reduction; test chip; Foot; Noise cancellation; Power supplies; Sleep; System-on-a-chip; Voltage control;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560331
