DocumentCode
1863317
Title
Partial scan: hardware and fault coverage trade-off
Author
Greene, Bruce S. ; Mourad, Samiha ; El-Ziq, Jacob
Author_Institution
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Volume
1
fYear
1998
fDate
18-21 May 1998
Firstpage
423
Abstract
In this paper we present an efficient algorithm for the selection of flip-flops for partial scan design. The algorithm determines the vertex set to open loops of length K or higher. Applying the algorithm to several ISCAS-89 benchmarks yields the best results for large circuits. Our results consistently indicated it is sufficient to scan a smaller set of flip-flops than the MVFS without significant sacrifice in fault coverage. We have applied the algorithm to RTL benchmarks with promising results
Keywords
automatic testing; circuit feedback; fault diagnosis; flip-flops; logic testing; sequential circuits; ISCAS-89 benchmarks; MVFS; RTL benchmarks; fault coverage; flip-flops; minimum feedback vertex set; partial scan design; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Feedback; Flip-flops; Hardware; Registers; Sequential analysis; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE
Conference_Location
St. Paul, MN
ISSN
1091-5281
Print_ISBN
0-7803-4797-8
Type
conf
DOI
10.1109/IMTC.1998.679822
Filename
679822
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