Title :
RTL design of parallel FFT with block floating point arithmetic
Author_Institution :
Kyushu Inst. of Technol., Iizuka
Abstract :
In modern wireless communication systems, FFT is one of the key components but requires wide numerical dynamic range. In order to satisfy both requirements of smaller chip size and wider numerical dynamic range, we employ block floating point arithmetic rather than neither fixed point one nor floating point one to implement real systems. In this paper, we show a RTL design result in terms of a radix-4 64-point FFT with parallel architecture using block floating point arithmetic. The results show that we can get more than 100 MHz clock frequency with 16-bit length or more even if we make use of FPGA devices.
Keywords :
fast Fourier transforms; floating point arithmetic; logic design; parallel architectures; radiocommunication; RTL design; block floating point arithmetic; parallel architecture; radix-4 64-point FFT; register transfer level design; smaller chip size; wider numerical dynamic range; wireless communication system; Bit error rate; Communication industry; Computer applications; Computer industry; Concurrent computing; Dynamic range; Floating-point arithmetic; MIMO; Parallel architectures; Wireless communication; Block floating point; FFT; Parallel architecture; RTL design;
Conference_Titel :
Soft Computing in Industrial Applications, 2008. SMCia '08. IEEE Conference on
Conference_Location :
Muroran
Print_ISBN :
978-1-4244-3782-5
Electronic_ISBN :
978-4-9904-2590-6
DOI :
10.1109/SMCIA.2008.5045973