• DocumentCode
    186519
  • Title

    Hardware reduction for RAM-based Moore FSMs

  • Author

    Kolopienczyk, Malgorzata ; Barkalov, Alexander ; Titarenko, Larysa

  • Author_Institution
    Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Zielona Gora, Poland
  • fYear
    2014
  • fDate
    16-18 June 2014
  • Firstpage
    255
  • Lastpage
    260
  • Abstract
    A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory block of FPGA chips. The method is based on replacement some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.
  • Keywords
    field programmable gate arrays; finite state machines; random-access storage; table lookup; FPGA chips; LUT; Moore FSM; embedded memory block; field-programmable gate arrays; finite state machine; hardware reduction; logic circuit; look-up table; multiplexer; random-access memory; Bismuth; Clocks; Field programmable gate arrays; Integrated circuit modeling; Logic circuits; Random access memory; Table lookup; EMB; FPGA; Moore FSM; RAM; design; logic circuit;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Human System Interactions (HSI), 2014 7th International Conference on
  • Conference_Location
    Costa da Caparica
  • Type

    conf

  • DOI
    10.1109/HSI.2014.6860485
  • Filename
    6860485
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=186519