Translation UML diagrams into Verilog

Author

Bazydlo, Grzegorz ; Adamski, Mariusz ; Stefanowicz, Lukasz

Author_Institution

Univ. of Zielona Gora, Zielona Gora, Poland

fYear

2014

fDate

16-18 June 2014

Firstpage

267

Lastpage

271

Abstract

The paper presents a method of using the UML state machine diagrams for specification of programs of logic controllers. The proposed method allows transformation from UML state machine diagram, using temporal Hierarchical Concurrent Finite State Machine (HCFSM) model, into Verilog hardware specification. The generated behavioral description in Hardware Description Language can afterwards be simulated, synthesized and implemented into e.g. FPGA device. A practical example illustrating the successive stages of the proposed method was also presented.

Keywords

Unified Modeling Language; finite state machines; formal specification; hardware description languages; HCFSM model; UML diagram translation; UML state machine diagrams; Verilog hardware specification; hardware description language; logic controller program specification; temporal hierarchical concurrent finite state machine; Automata; Control systems; Electric breakdown; Gold; Hardware design languages; Loading; Unified modeling language; Hierarchical Concurrent Finite State Machine (HCFSM); UML; Verilog; logic controller; state machine diagram;

fLanguage

English

Publisher

ieee

Conference_Titel

Human System Interactions (HSI), 2014 7th International Conference on

Conference_Location

Costa da Caparica

Type

conf

DOI

10.1109/HSI.2014.6860487

Filename

6860487