A quasi-planar approach to the monolithic integration of high-speed VCSEL and resonant photodetector arrays

Summary form only given. Monolithic arrays of VCSELs and resonant enhanced photodetectors (REPDs) can be integrated into optoelectronic circuits that perform useful functions in optical switching and wavelength division multiplexing (WDM) applications. For these and other optoelectronic interconnect applications, planarity is desirable for monolithic integration, and low power dissipation is required for dense arrays. To minimize power dissipation, oxide-confined VCSELs with small active areas and low operating currents are needed. In the standard (non-planar) technique for fabricating oxide-confined VCSELs, the active area is defined by the lateral wet oxidation of high aluminum content layers from the periphery of an etched mesa, with a typical oxidation length of >10 /spl mu/m. Minimizing the thermal and electrical resistance dictates a large mesa size, at the cost of a longer oxidation time and hence greater uncertainty in the final aperture size. The oxidation time and uncertainty can be reduced without sacrificing planarity or increasing the mesa size by introducing local oxidation centers (e.g., etched holes) from which multiple oxidation fronts can proceed to define an active aperture.