Title :
Fault coverage improvement and test vector generation for combinational circuits using spectral analysis
Author :
Ahmady, Maryam ; Sayedi, Sayed Masoud
Author_Institution :
ECE Dept., Isfahan Univ. of Technol., Isfahan, Iran
fDate :
April 29 2012-May 2 2012
Abstract :
This paper presents an algorithm for generating test vectors using static compaction. It employs spectral analysis to improve fault coverage and generate new test vectors based on the original ones. The technique can be used to improve fault coverage of RTL level vectors to detect gate level faults. Test generation, static compaction and fault coverage analysis are performed by using VHDL. The test generation algorithm generates a compact high fault coverage test vectors for combinational circuits described at different levels.
Keywords :
combinational circuits; fault tolerant computing; hardware description languages; logic testing; spectral analysis; RTL level vectors; VHDL; combinational circuits; fault coverage analysis; fault coverage improvement; gate level fault detection; high fault coverage test vectors; spectral analysis; static compaction; test generation algorithm; test vector generation; Algorithm design and analysis; Circuit faults; Combinational circuits; Compaction; Spectral analysis; Symmetric matrices; Vectors; Fault diagnosis; Spectral analysis; Test data compression;
Conference_Titel :
Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-1431-2
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2012.6334825