Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

Author

Tsai, W. ; Ragnarsson, L. ; Chen, P.J. ; Onsia, B. ; Carter, R.J. ; Cartier, E. ; Young, E. ; Green, M. ; Caymax, M. ; De Gendt, S. ; Heyns, M.

Author_Institution

Intel Corp., IMEC, Leuven, Belgium

fYear

2003

fDate

10-12 June 2003

Firstpage

21

Lastpage

22

Abstract

Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained. Sputtered TiN gate on the identical stacks yielded 0.82 nm EOT on NMOS devices using scaled chemical oxide interface with leakage current of 10/sup -3/ A/cm/sup -2/. CV hysteresis of TiN/HfO/sub 2/ was observed to decrease by an order of magnitude from the as deposited value to <10 mV after a 900/spl deg/C N/sub 2/ anneal.

Keywords

MOS capacitors; MOSFET; annealing; dielectric hysteresis; dielectric thin films; elemental semiconductors; hafnium compounds; leakage currents; semiconductor thin films; silicon; titanium compounds; 0.3 nm; 0.82 nm; 1 nm; 1.2 to 1.8 nm; 65 nm; 900 degC; CV hysteresis; HfO/sub 2/ dielectrics; Si-HfO/sub 2/; SiO/sub x/ interfaces; TiN-HfO/sub 2/; annealing; leakage current; modulating ozone concentration; poly NMOS capacitors; poly-Si/HfO/sub 2/ gate stacks; scaled chemical oxide interface; self-aligned transistors; sputtered TiN gate; Annealing; Capacitors; Chemical processes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; MOSFET circuits; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221066

Filename

1221066