Title :
FPGA implementation of discrete fractional Fourier transform
Author :
Prasad, M.V.N.V. ; Ray, Kailash Chandra ; Dhar, Anindya Sundar
Author_Institution :
Dept. of Electron. & Commun. Eng., Indian Inst. of Inf. Technol., Allahabad, India
Abstract :
Since decades, fractional Fourier transform has taken a considerable attention for various applications in signal and image processing domain. On the evolution of fractional Fourier transform and its discrete form, the real time computation of discrete fractional Fourier transform is essential in those applications. On this context, we have proposed new hardware architecture for implementing a Discrete Fractional Fourier Transform (DFrFT) which requires hardware complexity of O(4N), where N is transform order. This proposed architecture has been simulated and synthesized using verilogHDL, targeting a FPGA device (XLV5LX110T). The simulation results are very close to the results obtained by using MATLAB. The result shows that, this architecture can be operated on a maximum frequency of 217MHz.
Keywords :
computational complexity; digital arithmetic; discrete Fourier transforms; field programmable gate arrays; hardware description languages; signal processing; FPGA; MATLAB; discrete fractional Fourier transform; field programmable gate arrays; frequency 217 MHz; hardware complexity; image processing; signal processing; verilogHDL; Clocks; Computer architecture; Fourier transforms; Hardware; Radiation detectors; Read only memory; Registers; CORDIC; Discrete Fractional Fourier Transform; FPGA and Hardware Architecture;
Conference_Titel :
Signal Processing and Communications (SPCOM), 2010 International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-7137-9
DOI :
10.1109/SPCOM.2010.5560491
