DocumentCode
18664
Title
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9
Lower Energy/Acces
Author
Sinangil, M.E. ; Chandrakasan, Anantha P.
Author_Institution
NVIDIA, Bedford, MA, USA
Volume
49
Issue
1
fYear
2014
fDate
Jan. 2014
Firstpage
107
Lastpage
117
Abstract
This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g., video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9 × lower energy/access when compared with an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design.
Keywords
SRAM chips; amplifiers; application specific integrated circuits; integrated circuit design; 8T SRAM; application-specific SRAM design; array structure; bit-cell; output prediction; prediction-based reduced bit-line switching activity scheme; signal statistics; statistically gated sense amplifier approach; voltage scaling; Arrays; Correlation; Energy consumption; Motion estimation; Random access memory; Switches; System-on-chip; 10T-SRAM; Application-specific; correlation of data; energy-efficient SRAM; signal statistics;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2013.2280310
Filename
6605621
Link To Document