Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

Author

Lee, J.J. ; Wang, X. ; Bai, W. ; Lu, N. ; Liu, J. ; Kwong, D.L.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

2003

fDate

10-12 June 2003

Firstpage

33

Lastpage

34

Abstract

This paper describes improved memory characteristics of the Si nanocrystal memory devices by replacing the traditional SiO/sub 2/ with HfO/sub 2/ high-k dielectrics for the first time. Thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/, the fabricated device shows excellent programming efficiency and data retention characteristic. The single-electron charging effect is clearly observed at room temperature. It also shows superior data endurance up to 10/sup 6/ write/erase cycles.

Keywords

dielectric thin films; elemental semiconductors; hafnium compounds; integrated circuit modelling; integrated memory circuits; nanoelectronics; nanostructured materials; programmable circuits; silicon; single electron devices; 293 to 298 K; HfO/sub 2/ high-k tunneling dielectrics; Si nanocrystal memory device; Si-HfO/sub 2/; electron barrier height; memory properties; memory write/erase cycles; room temperature; single electron charging effect; Dielectric devices; Dielectric substrates; Dielectrics and electrical insulation; Electrons; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Nanocrystals; Tunneling; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221072

Filename

1221072