I/O design optimization flow for reliability in advanced CMOS nodes

Design-in-Reliability is becoming widely used as standard in Microelectronics Companies to qualify IPs reliability. In AMS applications, the quest for optimal design for manufacturability is difficult to handle because of the multiple dimensions of the problem (temperature, voltage, and yield). Furthermore, the strong request to take into account reliability constraints makes the task very challenging. In this context, a dedicated flow is developed and presented. Design-in-Reliability model is composed of all wear-out mechanisms (BTI, HCI and TDDB), whose integration in WiCkeD design flow opens the door for circuit analyses and sizing under reliability constraints. The flow has been proven using I/O interface cells as test cases. Results of circuit optimization are presented and benchmark of area overhead is also discussed. Several I/O designs have been implemented and validated by silicon measurements. First results showed a good agreement between measurements and simulation during degradation for both standard and optimized cells.