Effects of various assembly and reliability stresses on chip to package interaction

Author

Shiguo Rao ; Li Lin ; Xiaopeng Xu ; Bei Deng ; Borges, Ricardo

Author_Institution

Vitesse Semicond. Corp, Camarillo, CA, USA

fYear

2014

fDate

1-5 June 2014

Abstract

Systematic analysis of assembly and reliability stresses on chip to package interaction is performed. The novel modeling methodology employs multilevel sequential simulations to trace stress evolution, elasto-plasticity model to capture plastic strain accumulation, and actual GDS layout to evaluate BEOL reliability. The crack driving force is found to continue increasing during package assembly and field application due to plastic strain accumulation. A more comprehensive board level testing and analysis is recommended for better accessing long term package structure reliability.

Keywords

assembling; circuit reliability; elastoplasticity; electronics packaging; plastic deformation; stress analysis; BEOL reliability stress; GDS layout; assembly; board level testing; chip to package interaction; crack driving force; elastoplasticity model; long term package structure reliability; multilevel sequential simulation; plastic strain accumulation; Assembly; Flip-chip devices; Plastics; Silicon; Strain; Stress; Chip Package Interaction (CPI); Reliaility; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2014 IEEE International

Conference_Location

Waikoloa, HI

Type

conf

DOI

10.1109/IRPS.2014.6860607

Filename

6860607