Acceleration of chip - Package failures in temperature cycling

IC components experience temperature and power cycles during operation in their end use environments. They also experience cold temperature exposures during shipping. These temperature cycles influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. A complete assessment of the cumulative number of temperature cycles and temperature extremes from shipping/storage and through end-customer use is required to guarantee product performance and reliability. This paper will show data from accelerated temperature cycling on IC components and use these data to develop acceleration models for observed failure modes. These models will be used in conjunction with known use conditions to estimate lifetime requirements. These lifetime requirements will then be compared to JEDEC standards based requirements and a need for recalibration of these standards to more appropriate temperature cycle conditions and durations where will be highlighted. The influence of die package geometric factors on reliability performance will be shown. Some artifacts associated with stressing IC packages to extreme cold temperatures well outside of their intended use conditions will also be described.