A new methodology for copper/low-k dielectric reliability prediction

We propose a new methodology to de-convolute the intrinsic low-k material and interconnect geometric components from acceleration testing failure data, which allows a straightforward prediction of low-k failure time distributions at use conditions. Our analysis shows the intrinsic porous low-k failure time of Cu damascene interconnect will drop significantly when nominal Cu line spacing below 30 nm, with the influence of Cu geometric variability, low-k failure time further degraded depends on the lithography patterning technique used.