Title :
A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip
Author :
Fukai, T. ; Nakahara, Y. ; Terai, M. ; Koyama, S. ; Morikuni, Y. ; Suzuki, T. ; Nagase, M. ; Mineji, A. ; Matsuda, T. ; Tamura, T. ; Koba, F. ; Onoda, T. ; Yamada, Y. ; Komori, M. ; Kojima, Y. ; Yama, Y. ; Ikeda, M. ; Kudoh, T. ; Yamamoto, T. ; Imai, K.
Author_Institution :
Silicon Syst. Res. Lab., NEC Corp., Kanagawa, Japan
Abstract :
We have developed 65 nm-node CMOS technology for general-purpose system-on-a-chip (SoC), in which both standby and active power reductions are strongly required. With highly reliable triple gate oxide (1.3 nm, 1.6 nm and 3.2 nm) using low damage process, an average standby current can be reduced to one-fifth compared with conventional case. Gate pre-doping and RTA conditions were optimized to maintain on-current even with the supply voltage of 0.9 V. High-speed (HS) transistors show on-current of 680 /spl mu/A//spl mu/m for nFET and 240 /spl mu/A//spl mu/m for pFET with I/sub G/ of 13 nA//spl mu/m and I/sub OFF/ of 30 nA//spl mu/m. Low-gate-leakage (LGL) transistors show on-current of 490 /spl mu/A//spl mu/m for nFET and 175 /spl mu/A//spl mu/m for pFET with I/sub G/ of 0.8 nA//spl mu/m and I/sub OFF/ of 3 nA//spl mu/m. Gate oxide of all the above transistors exhibit tight TDDB distributions.
Keywords :
field effect transistors; rapid thermal annealing; semiconductor device reliability; system-on-chip; 0.9 V; 1.3 nm; 1.6 nm; 3.2 nm; 65 nm; CMOS technology; FET; RTA; damage process; gate leakage transistors; gate oxide; reliable triple gate oxide; semiconductor reliability; system-on-chip; CMOS technology; Leakage current; Maintenance; National electric code; Oxidation; Plasma temperature; Power system reliability; Resists; Strips; System-on-a-chip;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221097
