Voltage Ramp Stress Test to determine TDDB performance in SRAM vehicle

Author

Jae-Gyung Ahn ; Parameswaran, Sri ; Tsaggaris, Dean ; Chien-Wei Ku ; Ping-Chin Yeh ; Chang, Joana

Author_Institution

Si Technol. Group, Xilinx, Inc., San Jose, CA, USA

fYear

2014

fDate

1-5 June 2014

Abstract

We applied Voltage Ramp Stress Test (VRST) to an SRAM test vehicle and compared the obtained Vfail distribution with theoretical predictions from various TDDB failure criteria. Measured Vfail results are matched with the prediction from TDDB failure criterion of Ig/Ig0=1000 or more. We developed a numerical method to predict effective Igate with TDDB stress. It was applied to VRST condition and shows good agreement with measured data.

Keywords

SRAM chips; electric breakdown; failure analysis; integrated circuit reliability; integrated circuit testing; stress analysis; SRAM vehicle; TDDB failure criteria; TDDB performance; TDDB stress; VRST condition; time dependent dielectric breakdown; voltage ramp stress test; Current measurement; Electric breakdown; Logic gates; Probability density function; Random access memory; Stress; Stress measurement; Hi-K dielectric; Time Dependent Dielectric Breakdown (TDDB); Voltage Ramp Stress Test (VRST); effective gate current; failure criterion; progressive breakdown; standby current;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2014 IEEE International

Conference_Location

Waikoloa, HI

Type

conf

DOI

10.1109/IRPS.2014.6860617

Filename

6860617