DocumentCode
186717
Title
Impact of VLSI scaling on die qualification
Author
Haggag, A. ; Phillips, Malcolm ; Lee, J. K. Jerry
Author_Institution
Freescale Semicond., Inc., Austin, TX, USA
fYear
2014
fDate
1-5 June 2014
Abstract
As technology scales, the dominant die failure modes under voltage and environmental stress change to ones with higher acceleration factors suggesting industry standard electrical and environmental die qualification guidelines of stress tests are built with margin to cover mission life. Therefore running the full qualification helps demonstrate margin to the dominant failure modes yielding longer lifetime die.
Keywords
VLSI; failure analysis; integrated circuit reliability; stress analysis; VLSI scaling; acceleration factors; dominant die failure modes; electrical die qualification; environmental die qualification; environmental stress; lifetime die; stress tests; technology scaling; voltage stress; Acceleration; Logic gates; Moisture; Qualifications; Standards; Stress; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2014 IEEE International
Conference_Location
Waikoloa, HI
Type
conf
DOI
10.1109/IRPS.2014.6860619
Filename
6860619
Link To Document