(110)-surface strained-SOI CMOS devices with higher carrier mobility

In this paper, we have studied [110]-surface strained-SOI n- and p-MOSFETs with higher carrier mobility, according to the reduced interband/intervalley scattering and the smaller effective mass of carriers even in [110] strained-Si channel. The strained-Si channel has been formed on [110] relaxed-SGOI substrates, fabricated by the Ge condensation technique (25%) on a [110]-surface SOI substrate. It is demonstrated, for the first time, that the electron and the hole mobility enhancements of [110] strained-SOI devices amount to 23% and 50%, respectively, against to those of [110] unstrained-MOSFETs. Especially, the [110] hole mobility enhancement against the (100)-universal mobility amounts to 103%, which is much higher than that of [110] strained-SOIs (53%). Therefore, the unbalance between n- and p-channel current drivability can be reduced in [110] strained-SOI CMOS.