Double-sampling architectures

Aggressive technology scaling impacts dramatically parametric yield and reliability in advanced nanometric nodes, and can become showstoppers when moving deeper to the sub-10nm domain. To mitigate this issue various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of these approaches have certain fundamental drawbacks such as: large performance penalty, and/or large area and power penalty, and/or false positives and false negatives, and/or insufficient coverage of the failure mechanisms encountered in the deep nanometric domain. This paper presents an approach able to mitigate all these failures at low area, power, and performance penalties.